This application claims the benefit under 35 U.S.C. xc2xa7119 of Korean Patent Application No. 2002-12736, filed on Mar. 9, 2002, the entirety of which is hereby incorporated herein by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of preventing a ring defect, which may occur in an interlayer dielectric layer when forming conductive lines, such as bitlines, and a method of manufacturing the same.
2. Description of the Related Art
As the integration density of semiconductor devices has increased, research has been carried out more vigorously on a multilayered wiring layer technique which enables free and easy design of wiring layers and reduces wiring layer resistance and capacitance.
In the multilayered wiring layer technique, a complex resin material layer, such as a borophosphosilicate glass (BPSG) layer or a phosphosilicate glass (PSG) layer, or a spin on glass (SOG) layer is used as a planarization insulation layer in order to prevent a disconnection of upper wiring layers due to the unevenness of the lower wring layers. Since a SOG layer is weak in processes performed at a high temperature, it is used only in processes for forming upper metal wiring layers. A BPSG layer is used as a planarization layer in processes for forming lower transistors, bitlines, and capacitors.
A BPSG layer is composed of B2O3, P2O5, and SiO2 and is planarized by a predetermined heat treatment, for example, a flow process, after the deposition. The flow process may be performed at a high temperature of no less than 850xc2x0 C., and the temperature may be varied according to the components of a layer, and the process time and atmosphere of the flow process.
Here, a method of manufacturing a conventional semiconductor device having an interlayer dielectric layer formed of a BPSG layer will be described with reference to FIG. 1.
Referring to FIG. 1, an isolation layer 12 is formed on a semiconductor substrate 10. Next, a gate oxide layer 14, a conductive layer 16, and a capping layer 18 are sequentially deposited on the semiconductor layer 10 and are patterned to form a gate electrode structure (G). Next, a silicon nitride (SiN) layer is deposited on the semiconductor substrate 10 and is etched to form spacers 20 at either sidewall of the gate electrode structure (G) by blanket-anisotropic etching. Next, impurities are implanted into the semiconductor substrate 10 at either side of the gate electrode structure (G), thereby forming a junction region 25.
Next, in order to alleviate the step difference of the semiconductor substrate 10 caused by the gate electrode structure (G), a BPSG layer 30 is deposited on the semiconductor substrate 10 and is heat-treated at a predetermined temperature to be flowed. Next, an interlayer dielectric layer 32 is deposited on the flowed BPSG layer 30. The interlayer dielectric layer 32 is introduced to help the BPSG layer 30 to more strongly stick to conductive lines to be formed later.
Next, the inter layer dielectric layer 32 and the BPSG layer 30 are etched to expose the junction region 25, thereby forming a contact hole. Since the BPSG layer 30 has a higher etching rate than the interlayer dielectric layer 32, the BPSG layer 30 is etched much more than the interlayer dielectric layer 32 so that the sidewalls of the contact hole are formed as a bow shape, which is called a bowing phenomenon. In FIG. 1, xe2x80x9cbxe2x80x9d represents the portion of the interlayer dielectric layer, at which the bowing phenomenon occurs.
Next, contact spacers 35 are formed at the sidewalls of the contact hole. Next, the surface of the exposed junction region 25 is cleaned, and then a bitline 40 is formed to contact the exposed junction region 25.
However, since the conventional semiconductor device described above has the contact hole whose sidewalls are formed as a bow shape, the widths of the upper and lower portions of each of the contact spacers 35 are relatively narrow. In addition, if a cleaning process is performed before the formation of the bitline 40, a thickness of the interlayer dielectric layer 32 and a portion of the contact spacers 35 is washed away so that the interfacial surface between the BPSG layer 30 and the interlayer dielectric layer 32, and the interfacial surface between the BPSG layer 30 and the junction region 25 are exposed. Accordingly, a cleaning solution infiltrates into the interfacial surfaces and sweeps the BPSG layer 30 at the interfacial surfaces, thereby forming empty spaces in the BPSG layer 30.
As a result, as shown in FIG. 1, in the formation of the bitline 40, the conductive material of the bitline 40 is deposited in empty spaces in the BPSG layer 30 so that a ring defect 45 is generated in the BPSG layer 30.
The ring defect 45 may acts a path of leakage current and may cause a short circuit between the gate electrode structure (G, a wordline) and the bitline 40.
To solve the above-described problems, it is a first object of the present invention to provide a semiconductor device that is capable of preventing a short circuit from occurring between a wordline and a bitline.
It is a second object of the present invention to provide a semiconductor device which is capable of preventing a ring defect from occurring around a bitline contact area.
It is a third object of the present invention to provide a method of manufacturing the semiconductor device.
Accordingly, to achieve the first and second objects, there is provided a semiconductor device according to a first aspect of the present invention. The semiconductor device includes a semiconductor substrate having a junction region, a planarization layer having a first contact hole portion through which the junction region is exposed, an interlayer dielectric layer formed on the planarization layer and having a second contact hole portion extended from the first contact hole portion, and contact spacers formed at the sidewalls of the first and second contact hole portions. Here, the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate.
To achieve the first and second objects, there is provided a semiconductor device according to a second aspect of the present invention. The semiconductor device includes a semiconductor substrate having a junction region, a planarization layer having a first contact hole portion, through which the junction region is exposed, an interlayer dielectric layer formed on the planarization layer and having a second contact hole portion extended from the first contact hole portion, and contact spacers formed at the sidewalls of the first and second contact hole portions. Here, the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate, the interlayer dielectric layer has a slower etching rate than the planarization layer in an etchant used to form the first and second contact hole portions, and the contact spacers are formed of a material having a slower etching rate than the interlayer dielectric layer and the planarization layer in a cleaning solution.
Preferably, the upper edge of each of the contact spacers is located higher than the upper surface of one portion of the interlayer dielectric layer having a smaller thickness than the other portions of the interlayer dielectric layer.
The junction region includes a groove, through which the interface between the planarization layer and the semiconductor substrate is exposed.
Preferably, the width of the portion of the junction region exposed between the contact spacers is smaller than the original width of the junction region.
The sidewalls of the first contact hole portion are formed as a bow shape, and the contact spacers are formed to sufficiently fill the depth of the bowed regions of the sidewalls of the first contact hole portion.
Preferably, the width of the contact spacers is greater than the distance between one sidewall of the second contact hole portion and the corresponding sidewall of the first contact hole portion.
The planarization layer may be a BPSG layer, and the interlayer dielectric layer may be a medium oxide layer deposited at a temperature of 750-800xc2x0 C. The contact spacers may be formed of a silicon nitride (SiN) layer 18.
To achieve the third object, there is provided a method of manufacturing a semiconductor device. A semiconductor substrate having a junction region is provided. A planarization layer and an interlayer dielectric layer are sequentially deposited on the semiconductor substrate. A contact hole is formed to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer. Contact spacers are formed at the sidewalls of the contact hole. The surface of the semiconductor substrate is cleaned. A conductive line is formed to contact the exposed junction region. Here, the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate.
The interface between the planarization layer and the semiconductor substrate is exposed by excessively performing the etching process for forming the contact hole.
Preferably, the interlayer dielectric layer is formed of a material having a slower etching rate than the planarization layer in an etchant used to form the contact hole.
Preferably, the contact spacers are formed of a material having a slower etching rate than the interlayer dielectric layer and the planarization layer in a cleaning solution used to clean the surface of the semiconductor substrate.
For example, the planarization layer is formed of a BPSG layer, the interlayer dielectric layer is formed of a medium oxide layer deposited at a temperature of 750-800xc2x0 C., and the contact spacers are formed of a silicon nitride (SiN) layer.
The cleaning solution may be a mixed solution of a H2SO4 solution and a SC1 (NH4OH+H2O2+H2O) solution.
The planarization layer is etched more than the interlayer dielectric layer in the etching process for forming the contact hole so that a predetermined distance exists between one side edge of the interlayer dielectric layer and the corresponding side edge of the planarization layer and so that the width of the contact spacers is greater than the predetermined distance between one side edge of the interlayer dielectric layer and the corresponding side edge of the planarization layer.